1. Field of the Invention
The present invention relates to a sense amplifier circuit incorporated in a circuit having complementary data lines. More particularly, the present invention relates to a sense amplifier circuit incorporated in a dynamic random access memory (hereinafter referred to as a xe2x80x9cDRAMxe2x80x9d), etc., which requires a memory holding operation, which operates even with a low power supply voltage, which has a reduced power consumption, and which has a high data amplification speed.
2. Description of the Related Art
Recently, the increase in the application of semiconductor memory devices to portable equipments has prompted a reduction in the voltage of the semiconductor memory devices. Particularly, among other semiconductor memory devices, DRAMs, which require a memory holding operation, have a reduced voltage. The operating power supply voltage of some DRAMs is 2.5 V or less. For such DRAMs whose voltage has been reduced, the operation margin of a sense amplifier circuit has been an issue to be solved. The initial signal voltage AVsig from a memory cell of a sense amplifier circuit is represented by Expression 1 below.
xcex94Vsig=(1/2 Vcc)/(1+Cb/Cs)xe2x80x83xe2x80x83(Expression 1)
(Vcc: operating power supply voltage, Cb: bit line capacitance, Cs: memory cell capacitance)
As shown in Expression 1 above, a reduction in the operating power supply voltage Vcc reduces the initial signal voltage xcex94Vsig, thereby reducing the operation margin of the sense amplifier. In view of this, it has been proposed in the prior art to perform a sense amplification operation after the initial signal voltage xcex94Vsig is increased in the sense amplifier circuit (Heller, L. G., xe2x80x9cCross-Coupled Charge-Transfer Sense Amplifier,xe2x80x9d ISSCC Digest of Technical Papers, pp20-21, Febuary, 1979 (conventional example 1)).
FIG. 1 is a circuit diagram illustrating a sense amplifier circuit of conventional example 1, FIG. 2 is a block diagram of FIG. 1, and FIG. 3 is a timing chart illustrating the operation of the sense amplifier circuit of the conventional example 1.
The sense amplifier circuit of the conventional example 1 uses n-channel MOS transistors. The sense amplifier circuit includes a pre-amplifier including transistors T5 and T6, and an n-channel flip flop including transistors T3 and T4. The sources of the transistors T3 and T5 are connected to each other, and the gates thereof are connected to a node D2 in the sense amplifier. The sources of the transistors T4 and T6 are connected to each other, and the gates thereof are connected to a node D1 in the sense amplifier. A sense amplifier driving line V5 is connected to the drains of the transistors T3 and T4.
A sense amplifier potential pull-up signal line V2 is connected to the gate of each of the transistors T5 and T6 via a capacitor C1. The node D2 is provided between the transistor T4 and the transistor T6, and the source of a transistor T2 is connected to the node D2 therebetween. The transistor T2 is provided with a terminal 102 at its drain, and a sense amplifier driving potential (hereinafter referred to as xe2x80x9cVIxe2x80x9d) is applied to the terminal 102. Similarly, the node D1 is provided between the transistor T3 and the transistor T5, and the source of a transistor T1 is connected to the node D1 therebetween. The transistor T1 is provided with a terminal 102 at its drain, and VI is applied to the terminal 102.
A digit line D6 is connected to the drain of the transistor T6. The digit line D6 is connected to the sources of transistors T8 and T10. The drain of the transistor T8 is connected to a terminal 103. A digit line high potential (hereinafter referred to as xe2x80x9cVHxe2x80x9d) is applied to the terminal 103. A digit line pull-up signal line V3 is connected to the gate of the transistor T8, and a digit line pull-down signal line V4 is connected to the gate of the transistor T10.
A memory cell including one transistor 100 and one capacitor 101 is connected to the digit line D6, and a word line WL is connected to the memory cell. The sense amplifier circuit is incorporated in a DRAM, and has a left-right symmetric configuration. A digit line D5 is connected to the drain of the transistor T5. The configurations of transistors T7 and T9 and the memory cell which are connected to the digit line D5 are the same as those which are connected to the digit line D6, and thus will not be further described below.
As illustrated in FIG. 2 which is a block diagram of the conventional example 1, an n-channel flip flop 110, a precharge circuit 111, and a digit line VH precharge circuit 112 for precharging the digit lines D5 and D6 to the potential of VH, are connected in parallel between complementary bit lines BLT0 and BLN0. The transistor T5 is provided along the bit line BLT0 between the precharge circuit 111 and the digit line VH precharge circuit 112, and the transistor T6 is provided along the bit line BLN0 therebetween. The gate of the transistor T5 is connected to the complementary bit line BLN0, and the gate of the transistor T6 is connected to the bit line BLT0.
Next, the operation of the conventional example 1 will be described. As illustrated in FIG. 3, at the beginning of the operation, the digit lines D5, D6 are precharged from GND to VI-Vth (transistor threshold potential) via the transistors T1 and T5, and T2 and T6, respectively. As the potential of the word line WL transitions to a high level, a large potential difference occurs between the nodes D1 and D2 due to a charge transfer. VI-Vth is about VH/2. Thus, the capacitance of the digit lines D5 and D6 is greater than that of the nodes D1 and D2.
Then, when the word line WL rises and if the digit line D6 side is at a low level, the gate-source potential VGS of the transistor T6 becomes greater than the threshold potential Vth of the transistor T6, thereby turning ON the transistor T6, whereby a charge moves from the node D2 to the digit line D6. At this time, on the node D2 side, due to the capacitance difference between the digit line D6 and the node D2, a potential difference greater than that occurring on the digit line D6 side occurs when the word line WL rises.
Then, when the potential of the sense amplifier pull-up signal line V2 transitions to the high level, the potential difference between the nodes D1 and D2 has a magnitude which is at least Vth or more of the transistors T5 and T6 (n-channel transistors) due to the capacitor C1. Thereafter, the digit lines D5 and D6 are precharged to VH by the transistors T7 and T8, respectively, and the potentials at the nodes D1 and D2 and the digit lines D5 and D6 are amplified to the high level or the low level by turning ON the transistors T3 and T4 while bringing the potential of the sense amplifier driving line V5 to the low level so as to activate the n-channel flip flop. Then, at the end of the operation, the potential of the word line WL is brought to the low level and the potential of the sense amplifier driving line V5 is brought to the high level so as to turn OFF the n-channel flip flop, and the potential of the digit line pull-down signal line V4 is brought to the high level so as to reduce the potential of the digit lines D5 and D6 to GND.
As another method for sense-amplifying an initial voltage signal, for example, Tsukude, M., et al. xe2x80x9cA 1/2 V to 3.3 V Wide-Voltage-Range DRAM with 0.8 V Array operation,xe2x80x9d ISSCC Digest of Technical Papers, pp66-67, Febuary, 1997 (conventional example 2) has been proposed in the art. FIG. 4 is a circuit diagram illustrating a sense amplifier circuit of conventional example 2, FIG. 5 is a block diagram of FIG. 4, and FIG. 6 is a timing diagram illustrating the operation of the sense amplifier circuit of the conventional example 2.
The sense amplifier circuit of the conventional example 2 has a CMOS configuration, and includes two p-channel flip flops 123, one n-channel flip flop 124, sense amplifier (hereinafter referred to also as xe2x80x9cSAxe2x80x9d) section precharge transistors T13 and T14, and digit line-SA separation transistors T11 and T12.
A memory cell including one transistor 127 and one capacitor 128 is connected to a digit line BLT0. A word line WL is connected to the gate of the transistor 127. A digit line BLN0 which is opposing and complementary to the digit line BLT0 is provided. As the digit line BLT0, the digit line BLN0 is provided with a memory cell (not shown). A digit line BLT1 which extends collinearly with the digit line BLT0 is provided. A digit line BLN1 which is opposing and complementary to the digit line BLT1 is provided. Data transfer lines IOT and ION are provided between the digit lines BLT0 and BLN0. The data transfer line IOT and the digit line BLT0 are connected to each other via a transistor 125, and the data transfer line ION and the digit line BLN0 are connected to each other via a transistor 126. A column selection line YSW is connected to the gates of the transistors 125 and 126.
The digit line BLT0 is provided with the transistor T11, and the digit line BLN0 is provided with the transistor T12. A digit line connection signal line SGO is connected to the gates of the transistors T11 and T12. Similarly, the digit line BLT1 and the digit line BLN0 are provided with transistors T15 and T16, respectively, and a digit line connection signal line SG1 is connected to the gates of the transistors T15 and T16.
In a place adjacent to the memory cell, the sources of transistors 121 and 120 are connected to the digit line BLT0 and the digit line BLN0, respectively, and the source and the drain of a transistor 122 are connected to the digit lines BLT0 and BLN1. A digit line precharge signal line BREQ0 is connected to the gates of the transistors 120, 121 and 122. A precharge line 131 is connected to the sources of the transistors 120 and 121.
Moreover, the p-channel flip flop 123 is provided between the digit lines BLT0 and BLN0, and is connected to the digit lines BLT0 and BLN0. The flip flop 123 is connected to a power supply voltage line 134. The drains of the transistors T13 and T14 are connected to the digit lines BLT0 and BLN0, respectively. An internal power supply voltage line 132 is connected to the sources of the transistors T13 and T14. A sense amplifier precharge line 133 is connected to the gates of the transistors T13 and T14. The n-channel flip flop 124 is provided between the digit line BLT0 and the digit line BLN0. The flip flop 124 is connected to a ground potential line GND, and is provided with nodes E0 and E1.
The flip flop 123 and the transistors 120, 121 and 122 are provided between the digit line BLT1 and the digit line BLN1, as those provided between the digit line BLT0 and the digit line BLN0. A digit line precharge signal line BREQ1 is connected to the gates of the transistors 120, 121 and 122.
As illustrated in FIG. 5 which shows the conventional example 2 in a simplified form, the n-channel flip flop 124, a precharge circuit 130 and the p-channel flip flop 123 are connected in parallel between the digit line BLT0 and the digit line BLN0. The digit lines BLT0 and BLN0 are amplified by applying a signal whose potential transitions from GND to VSG to a digit line connection signal line SG.
Next, the operation of the conventional example 2 will be described. As illustrated in FIG. 6, before the sense amplifier circuit starts operating, the potentials of the digit line precharge signal lines BREQ0 and BREQ1 transition to Vcc, and the transistors 120 and 121 are turned ON, whereby the digit lines BLT0, BLN0, BLT1 and BLN1 are precharged to xc2xd Vcc. Moreover, the potential of the sense amplifier precharge line 133 transitions to VBOOT, and the SA section is precharged to a potential of Vcc(1+xcex3). Then, upon the start of the operation, the potential of the precharge line 133 transitions to the low level, thereby turning OFF the SA section precharge transistors T13 and T14, and the potential of the word line WL transitions to the high level, whereby the cell data is output to the digit lines BLT0 and BLN0. Then, by setting the potential of SG0 to the VSG potential, a charge transfer occurs from the nodes E0 and E1 to the digit lines BLT0 and BLN0, respectively, thereby causing a large potential difference between the nodes E0 and E1. Thereafter, the n-channel flip flop 124 and the p-channel flip flop 123 are activated, thereby amplifying the potential difference between the nodes E0 and E1 and the potential difference between the digit lines BLT0 and BLN0, respectively. Then, at the end of the operation of the sense amplifier circuit, the potential of the word line WL transitions to the low level, the SG0 potential to the GND level, and the potential of the precharge line 133 to the high level, thereby precharging the respective sections.
However, the conventional example 1 has the following problem. As described above, a digit line signal amount is generated after the digit lines D5 and D6 are precharged to a potential in the vicinity of VI-Vth via the transistors T5 and T6, respectively (VI precharge in the sense amplifier). Therefore, data amplification is started while either one of the transistors T5 and T6 is close to an ON state or an OFF state. Thus, in the conventional example 1, the xc2xd Vcc precharge method is not used, whereby the power consumption is increased because the digit lines D5 and D6 are brought up from GND to the VH level during operation. Moreover, the data read operation is slow because, for example, the pre-amplification operation by a precharge operation of the digit lines D5 and D6 or a charge transfer operation takes a long time, and the data low side is sensed/amplified after the data high side is charged.
On the other hand, in the conventional example 2, a digit line signal amount is generated from the digit lines BLT0, BLN0, BLT1 and BLN1 which have been precharged to a potential of xc2xd Vcc. Then, data amplification is started while either one of the transistors T11 and T12 is close to an ON state or an OFF state by bringing the gate potentials of the transistors T11 and T12 up to the appropriately set VSG potential. Thus, the conventional example 2 uses the xc2xd Vcc precharge method, thereby resulting in a power consumption smaller than that of the conventional example 1. However, it is necessary to increase the internal power supply potential VSG, Vcc(1+xcex3) for driving the sense amplifier. Moreover, since p-channel transistors are arranged on both sides of an n-channel transistor, the area of the circuit increases by the area required for n-well separation. Furthermore, since a fine control on the level of the internal power supply potential VSG is necessary, the circuit is susceptible to variations in VSG-Vth of a transistor, and the digit line signal amount may possibly be reduced.
Furthermore, both in the conventional example 1 and the conventional example 2, it is necessary to perform the data amplification operation through a charge transfer by operating a transistor with a voltage in the vicinity of the threshold voltage thereof.
An object of the present invention is to provide a sense amplifier circuit which has a sufficient sensing margin even when the power supply voltage is reduced, which has a reduced power consumption, and in which the influence of variations in the threshold voltage of a transistor can be reduced.
A sense amplifier circuit according to a first aspect of the invention is a sense amplifier circuit for amplifying a signal difference between complementary data lines of a semiconductor memory device. The sense amplifier circuit comprises a converting unit which converts a difference between respective currents flowing along the complementary data lines into a voltage difference: and amplifying unit which amplifies the voltage difference to a logic level so as to write the logic level back to the complementary data lines.
In the first aspect of the invention, the difference between the currents flowing along the respective complementary data lines is converted into a voltage difference, and the voltage difference is amplified to a logic level, after which a potential of the high or low level is written back to the complementary data lines. As a result, even if the operating voltage of the semiconductor memory device is reduced, thereby reducing the data signal amount of the data lines, it is possible to obtain a sufficient data signal amount.
A sense amplifier circuit according to a second aspect of the invention is a sense amplifier circuit for amplifying a signal difference between complementary data lines of a semiconductor memory device. The sense amplifier circuit comprises: a current difference amplification circuit for amplifying a potential difference between the complementary data lines by using a difference between respective currents flowing into the complementary data lines which occurs due to the potential difference between the complementary data lines; a pair of nodes which are connected to the current difference amplification circuit for outputting the amplified potential difference; a voltage difference amplification circuit connected to the nodes for amplifying the potential difference between the nodes into a logic level; a precharge circuit connected to the nodes for causing a current to flow from the current difference amplification circuit to the complementary data lines; and a sense amplifier connection circuit connected to the nodes and the complementary data lines for electrically connecting or disconnecting the nodes to or from the complementary data lines.
In the second aspect of the invention, the precharge circuit is used to cause a current to flow to the complementary data lines which already have a signal difference (potential difference) therebetween, after which a charge is transferred from the nodes to the complementary data lines and the potential difference between the complementary data lines is amplified by the current difference amplification circuit by using the current difference between the complementary data lines, thereby generating a large data signal amount at the nodes. Then, the potential difference is further amplified by the voltage difference amplification circuit to a logic level, after which the nodes and the complementary data lines are electrically connected to each other by the sense amplifier connection circuit, and data is written by applying a high or low potential to the complementary data lines. Thus, even if the power supply voltage of the semiconductor memory device is reduced, thereby reducing the signal difference of the complementary data lines, it is possible to generate a sufficient data signal amount at the nodes and to amplify the potential difference between the complementary data lines at a high speed.
In the sense amplifier circuit, for example, the current difference amplification circuit includes: a first transistor whose source is connected to one of the complementary data lines, whose drain is connected to one of the nodes, and whose gate is connected to the other one of the nodes; and a second transistor whose source is connected to the other one of the complementary data lines, whose drain is connected to the other one of the nodes, and whose gate is connected to the one of the nodes. The precharge circuit includes: a third transistor whose drain is connected to the one of the nodes, whose source is connected to a precharge power supply line of the nodes, and whose gate is connected to an activation signal line to which a precharge activation signal is input; a fourth transistor whose drain is connected to the other one of the nodes, whose source is connected to the precharge power supply line of the nodes, and whose gate is connected to the activation signal line to which the precharge activation signal is input; and a fifth transistor whose source and drain, or drain and source, are connected to the nodes, respectively, and whose gate is connected to the activation signal line to which the precharge activation signal is input. The voltage difference amplification circuit includes: a sense amplifier low side amplification circuit, including: a sixth transistor whose drain is connected to the one of the nodes, whose source is connected to a sense amplifier low side driving line, and whose gate is connected to the other one of the nodes; and a seventh transistor whose drain is connected to the other one of the nodes, whose source is connected to the sense amplifier low side driving line, and whose gate is connected to the one of the nodes; and a sense amplifier high side amplification circuit, including: an eighth transistor whose drain is connected to the one of the nodes, whose source is connected to a sense amplifier high side driving line, and whose gate is connected to the other one of the nodes; and a ninth transistor whose drain is connected to the other one of the nodes, whose source is connected to the sense amplifier high side driving line, and whose gate is connected to the one of the nodes. The sense amplifier connection circuit includes a tenth transistor and an eleventh transistor for connecting or disconnecting the complementary data lines to or from the nodes.
Alternatively, in the sense amplifier circuit, for example, the current difference amplification circuit includes: a first transistor whose source is connected to the one of the complementary data lines, whose drain is connected to the one of the nodes, and whose gate is connected to the other one of the nodes; and a second transistor whose source is connected to the other one of the complementary data lines, whose drain is connected to the other one of the nodes, and whose gate is connected to the one of the nodes. The precharge circuit includes: a third transistor whose drain is connected to the one of the nodes, whose source is connected to a precharge power supply line of the nodes, and whose gate is connected to an activation signal line to which a precharge activation signal is input; a fourth transistor whose drain is connected to the other one of the nodes, whose source is connected to the precharge power supply line of the nodes, and whose gate is connected to the activation signal line to which the precharge activation signal is input; and a fifth transistor whose source and drain, or drain and source, are connected to the nodes, respectively, and whose gate is connected to the activation signal line to which the precharge activation signal is input. The voltage difference amplification circuit includes: a sense amplifier low side amplification circuit, including: a twelfth transistor whose drain is connected to the one of the nodes, whose source is connected to a sense amplifier low side driving line, and whose gate is connected to the other one of the nodes; and a thirteenth transistor whose drain is connected to the other one of the nodes, whose source is connected to the sense amplifier low side driving line, and whose gate is connected to the one of the nodes; and a restore circuit, including: a first coupling capacitor and a second coupling capacitor whose ohe end is connected to a restore driving signal line; a fourteenth transistor whose drain is connected to the one of the nodes, whose source is connected to the other end of the first coupling capacitor, and whose gate is connected to a power supply voltage line; a fifteenth transistor whose drain is connected to the other one of the nodes, whose source is connected to the other end of the second coupling capacitor, and whose gate is connected to the power supply voltage line; a sixteenth transistor whose drain is connected to a sense amplifier high side driving line, whose source is connected to the one of the complementary data lines, and whose gate is connected to the other end of the first coupling capacitor; and a seventeenth transistor whose drain is connected to the sense amplifier high side driving line, whose source is connected to the other one of the complementary data lines, and whose gate is connected to the other end of the second coupling capacitor. Here, the sense amplifier connection circuit includes a tenth transistor and an eleventh transistor for connecting or disconnecting the complementary data lines to or from the nodes.
For example, after a potential difference between the nodes is amplified to a logic level by the voltage difference amplification circuit, the sense amplifier connection circuit electrically connects the complementary data lines to the nodes.
Alternatively, after a potential difference between the nodes is amplified to a logic level by the voltage difference amplification circuit, the sense amplifier connection circuit may electrically connect the complementary data lines to the nodes while bringing a potential of one of the complementary data lines which has a lower potential to a low level and further amplifying a potential of one of the complementary data lines which has a higher potential.
Moreover, it is preferred that the sense amplifier connection circuit electrically connects one of the nodes to one of the complementary data lines, thereafter electrically connecting the other one of the nodes to the other one of the complementary data lines after a potential difference between the nodes is amplified to a logic level by the voltage difference amplification circuit.
Furthermore, it is preferred that there is further provided a booster circuit for boosting a voltage of each of the complementary data lines to a potential which is one half of a power supply voltage of the semiconductor memory device.